Conventionally, a liquid crystal display device provided with a charge pump circuit is known in which the charge pump circuit steps up an input voltage and outputs the stepped-up voltage as an output voltage. Such a charge pump circuit can step up a voltage with a relatively simple circuit.
A liquid crystal display device provided with a charge pump circuit is proposed in which the charge pump circuit forms a control voltage to stabilize the above-mentioned stepped-up voltage based on a comparison between a detection voltage corresponding to the stepped-up voltage formed by the charge pump circuit and a reference voltage and forms a display voltage through a stabilized stepped-up voltage (e.g., see Patent Document 1).
FIG. 9 is a circuit diagram illustrating an embodiment of a conventional charge pump circuit (step-up charge pump circuit) used for such a liquid crystal display device, etc.
The charge pump circuit 900 steps up an input voltage Vin and outputs the stepped-up voltage as an output voltage Vout. Such a charge pump circuit 900 is constructed of two switching elements S1 and S2 and a capacitor Cp. The switching element S1 and switching element S2 are constructed by combining an n-type transistor and p-type transistor. In the charge pump circuit 900, the switching element S1 is an n-type transistor and the switching element S2 is a p-type transistor. The capacitor Cp is connected between these switching element S1 and switching element S2.
A main power supply Vdd is connected to the switching element S1 and the input voltage Vin is supplied to the charge pump circuit 900. An output terminal 901 is connected to the switching element S2 and charge (output voltage Vout) stored in the capacitor Cp is output from the output terminal 901. A load 902 is connected to the output terminal 901. The load 902 is, for example, a liquid crystal display element and a current IL is required to drive the load 902. A capacitor CL for ripple elimination is connected to the output terminal 901.
Terminals (not shown) provided for the two switching elements S1 and S2 (hereinafter referred to as ‘switching element terminals’) and the terminal of the capacitor Cp not connected to the switching elements S1 and S2 (hereinafter referred to as ‘capacitor terminal’) are used as clock signal input terminals to which clock signals with mutually opposite phases are applied. Here, a clock signal defined by phase Φ is applied to the former and a clock signal defined by phase/Φ (┌/┘ denotes logical inversion) is applied to the latter. FIG. 9 shows that the clock signal corresponding to the former is in a high level state and the clock signal corresponding to the latter is in a low level state.
When the clock signals are in the states shown in the figure, the switching element S1 is electrically on, while the switching element S2 is electrically off. On the other hand, the capacitor Cp is in a low-potential state. Thus, charge corresponding to the input voltage Vin moves to the capacitor Cp.
Then, when the phase of the clock signal is inverted, the charge stored in the capacitor Cp moves to the load 902 side. That is, when the clock signal corresponding to the switching element terminal is inverted to a low level and the clock signal corresponding to the capacitor terminal is inverted to a high level, the switching element S1 becomes electrically off and the switching element S2 becomes electrically on. On the other hand, the capacitor Cp is in a high-potential state. For this reason, the charge stored in the capacitor Cp moves from the output terminal 901 to the load 902 side.
Thus, the operation of moving the charge to the capacitor Cp and the operation of moving the charge to the load 902 side are repeated.
[Patent Document 1] Unexamined Japanese Patent Publication No. 2003-295830 (FIG. 3)